1. Field of the Invention
Embodiments of the invention relate to a semiconductor integrated circuit device.
2. Description of the Related Art
In semiconductor integrated circuit (IC) devices such as a semiconductor physical quantity sensor device that is equipped with a physical quantity sensor (e.g., a pressure sensor or accelerometer) and used in various types of devices such as those for automobiles, medical purposes, manufacturing purposes, and the like, output characteristics of the physical quantity sensor are adjusted by trimming. The precision of the physical quantity sensor is increased by trimming, for example, the sensitivity, temperature characteristics, offset, etc.
A conventional laser trimming technique for performing such trimming is disadvantageous in that even when output characteristics vary at an assembly process after trimming, readjustment is not possible. Therefore, recently, an electrical trimming technique is employed that uses Erasable Programmable Read Only Memory (EPROM) and can adjust output characteristics after the assembly process has been completed.
As a semiconductor integrated circuit device that performs electrical trimming using EPROM, a device has been proposed that measures sensor output while gradually varying provisional data stored by a shift register to thereby set trimming data that obtains a desired sensor output. The device further stores the trimming data to the EPROM, and uses the stored trimming data to adjust the sensor output (for example, refer to Japanese Patent Application Laid-Open Publication No. 2002-310735).
Nonetheless, in electrical trimming by EPROM, a problem arises in that bit corruption occurs where data written to the EPROM changes (bits are inverted) consequent to leakage of charge accumulated in the EPROM or charge injection into the EPROM.
Thus, a redundancy design is commonly adopted where two or more EPROMs storing identical data are provided for each bit and the logical sum (OR) or majority function is taken, whereby the data is prevented from varying even when charge leakage or charge injection occurs at one of the EPROMs storing identical data.
Configuration of a conventional semiconductor integrated circuit device will be described. FIG. 5 is a plan view of an example of a planar layout of a conventional semiconductor integrated circuit device. A memory circuit of the conventional semiconductor integrated circuit device depicted in FIG. 5 is produced on an IC chip (semiconductor chip) 100 and includes EPROMs 101, switches (Sw) 102, shift registers (SR) 103, and OR circuits 104. In a peripheral portion of the IC chip 100, a ground wiring line 113 is disposed along a periphery of the IC chip 100, in a substantially rectangular shape and is connected to a ground terminal (ground pad) 111. Farther inward on the IC chip 100 than the ground wiring line 113, a write_voltage wiring line 114 is disposed along a periphery corresponding to three sides of the IC chip 100, is disposed in a substantially rectangular shape having one opened portion (substantially a “U” shape or substantially a “” shape), and is connected to write_voltage terminal (write_voltage pad) 112.
Between the ground wiring line 113 and the write_voltage wiring line 114, sets of at least two EPROMs 101 that store identical data (1 bit) and form a 1-bit storage region 5 (see, e.g., FIG. 1) of the memory circuit are connected in parallel corresponding to the storage capacity (bit count) of the memory circuit. Connection of a set of EPROMs 101 that store identical data (1 bit) and form a 1-bit storage region 5 of the memory circuit to a single OR circuit 104 achieves a redundancy design with respect to charge leakage of the EPROMs 101. In FIG. 5, an example is depicted where the storage capacity of the memory circuit is 2n (n: natural number) bits, and for each bit, two EPROMs 101 (a and b in the drawing; and 101a and 101b hereinafter) are provided. In the drawing, the bit numbers assigned to the EPROMs 101a, 101b are 1, 2, 3, 4, . . . , n−3, n−2, n−1, n, n+1, n+2, n+3, n+4, . . . , 2n−3, 2n−2, 2n−1, 2n. Each OR circuit 104 outputs the logical sum of the data in the EPROMs 101a, 101b connected thereto, whereby output Data (i) (i=1, 2, . . . , 2n−1, 2n) from the OR circuit 104 is maintained even when charge leakage occurs at one of the EPROMs among the EPROM 101a, 101b. 
When redundancy related to data retention characteristics of the EPROMs 101 is enhanced by combining multiple EPROMs 101 in this manner, increases in the area of the IC chip 100 are typically suppressed by combining components that are disposed near each other (e.g., adjacently) on the IC chip. For example, the EPROMs 101 are disposed between the ground wiring line 113 and the write_voltage wiring line 114, along the ground wiring line 113. The same data is stored to adjacent EPROMs 101a, 101b. FIG. 5 depicts a state where the EPROMs 101 are disposed in a row so as to be along peripheries corresponding to a first pair of opposite sides of the IC chip 100. The switches 102 that supply drain voltage to a pair of EPROMs 101a, 101b, the shift registers 103 that control the ON and OFF state of these switches 102, and the OR circuit 104 connected to the pair of EPROMs 101a, 101b, are disposed close to the corresponding pair of EPROMs 101a, 101b. 
The drain of an EPROM 101 is connected to the write_voltage wiring line 114 via a switch 102 and the source is connected to the ground wiring line 113. The EPROM 101 is a metal oxide semiconductor field effect transistor (MOSFET) in a flooding (floating) state where the gate is open (not depicted). On the gate in the flooding state (flooding gate), a control gate is provided via an oxide film. Therefore, when data is written to the EPROM 101 and the switch 102 is turned ON, the predetermined EPROM 101 and the write_voltage terminal 112 are caused to conduct, write_voltage is applied to the write_voltage terminal 112, and high voltage of a threshold voltage or greater is applied to the control gate of the EPROM 101. As a result, charge is injected into and accumulates in the flooding gate of the predetermined EPROM 101.
Configuration of another example of a conventional semiconductor integrated circuit device will be described. FIG. 6 is a plan view of another example of a planar layout of a conventional semiconductor integrated circuit device. As depicted in FIG. 6, a device has been proposed in which a portion of the ground wiring line (hereinafter, first ground wiring line) 113 is extended so as to turn back inwardly on the IC chip, and all of the EPROMs 101 are connected to this extended portion (hereinafter, second ground wiring line) 115. By making the distance from the ground terminal 111 on the ground wiring line of the EPROM 101 long and by making the parasitic resistance by the ground wiring line (the first and second ground wiring lines 113, 115) of the EPROM 101 high, tolerance with respect to noise (hereinafter, external noise) that enters the wiring line from an external source is increased. Excluding the positions of the connection points on the ground wiring line of the EPROMs and the second ground wiring line 115, the configuration of the conventional semiconductor integrated circuit device depicted in FIG. 6 is identical to that of the conventional semiconductor integrated circuit device depicted in FIG. 5.
As a semiconductor integrated circuit device for which tolerance to external noise has been increased, a device has been proposed in which a protective function against external noise of the EPROM is provided whereby unintended writing (errant writing) to the EPROM by external noise is prevented (for example, refer to Japanese Patent Application Laid-Open Publication Nos. 2009-231650, 2005-026307, 2012-209526, and 2012-160611).
Nonetheless, with the conventional semiconductor integrated circuit devices described above, the following problems arise when redundancy design against charge leakage and charge injection of the EPROMs is performed and components disposed at mutually close positions on the IC chip (e.g., adjacent EPROMs 101) are combined to suppress increases in the area of the IC chip 100.
Natural deterioration, oxide film defects, and external noise may cause charge leakage of the EPROMs 101, while external noise may cause charge injection of the EPROMs 101. Charge leakage consequent to natural deterioration occurs similarly at all of the EPROMs 101. Therefore, even if the redundancy design against charge leakage of EPROMs 101 is performed as depicted in FIG. 5, redundancy with respect to data retention characteristics of the EPROMs 101 is not substantially achieved. The redundancy design against charge leakage of the EPROMs 101 depicted in FIG. 5 is a configuration in which identical data is written to adjacent EPROMs 101 (101a, 101b) and the EPROMs 101 are connected to a single OR circuit 104.
Meanwhile, charge leakage of the EPROMs 101 consequent to oxide film defects occurs as a result of current leaked by fine crystal defects that have a certain probability of being inside the oxide film. Therefore, the probability that both of the adjacent EPROMs 101 have an oxide film defect and low data retention characteristics is not substantially different from the probability of the same between EPROMs 101 that are not adjacent to each other. Therefore, redundancy with respect to the data retention characteristics of the EPROMs 101 is obtained by performing the redundancy design against charge leakage of the EPROMs 101 as depicted in FIG. 5.
Nonetheless, the adjacent EPROMs 101 are adversely affected by external noise to the same extent and therefore, charge leakage and charge injection of the EPROMs 101 occurs at the same extent in each EPROM 101. Adverse effects of external noise include errant writing to the EPROM 101 consequent to disposal near components that generate noise such as near external components and the wiring thereof and the terminals 111, 112; and errant operation consequent to a ground potential increase or write_voltage caused by electromagnetic induction of a coil resulting from disposal near a component that includes a coil such as an igniter. Therefore, redundancy with respect to the data retention characteristics of the EPROMs 101 is not obtained even when the redundancy design against charge leakage of the EPROMs 101 is performed as depicted in FIG. 5.
Further, although measures such as providing a protective function (refer to Japanese Patent Application Laid-Open Publication Nos. 2009-231650, 2005-026307, 2012-209526, and 2012-160611) and increasing the parasitic resistance by the ground wiring lines 113, 115 of the EPROMs 101 (refer to FIG. 6) are effective for enhancing tolerance against certain external noise, these measures are not effective against all external noise. Therefore, a tradeoff exists where it may be better to not implement the measures above to improve tolerance with respect to other external noise and it is difficult to improve tolerance against all external noise to prevent charge leakage and charge injection of the EPROM 101.